(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving copper interconnect reliability performance by improving the adhesion between the copper of the copper interconnect and a barrier layer.
(2) Description of the Prior Art
Performance improvements of Integrated Circuits are typically achieved by device miniaturization, which concurrently results in increasing the packaging density of the created Integrated Circuits. Methods and materials that are applied for interconnecting Integrated Circuits are therefore becoming an increasingly more importance part of creating packaged semiconductor devices.
The selection of insulation materials and the selection of the materials that are used for the creation of interconnect metal continue to be explored as part of a continuing effort to improve device performance. In this respect for instance methods and materials are explored that allow for the creation of low-k dielectric interfaces between adjacent layers of interconnect metal. In addition, the materials that are used for the creation of the interconnect metal, such as interconnect vias and interconnect traces, continues to present a challenge.
For the use as an interconnect medium, copper has increasingly gained acceptance and is increasingly being used for this purpose. Copper is known to have low cost and a low resistivity, copper however has a relatively large diffusion coefficient into silicon dioxide and silicon. Copper from an interconnect may diffuse into a surrounding silicon dioxide layer, causing the dielectric to become conductive and decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects are therefore conventionally encapsulated by at least one layer of diffusion barrier material that prevents diffusion of the copper into the surrounding dielectric such as a layer of silicon dioxide. Silicon nitride is frequently used as a diffusion barrier layer for copper, the disadvantage of this approach however is that metal interconnects preferably should not lie over a silicon nitride layer since the silicon nitride layer has a high dielectric constant when compared with silicon dioxide, causing an undesirable increase in the capacitance between the interconnect metal and the underlying substrate.
Copper is also known to have low adhesive strength to various insulating layers and is difficult to pattern by masking and etching a blanket layer of copper in order to create intricate structural circuit elements.
To create conductive interconnect lines and vias, the damascene or dual damascene process is frequently used. For the creation of Very and Ultra Large Scale Integrated devices using the dual damascene process, a layer of insulating or dielectric material is patterned and developed, creating several thousand openings there-through for conductive interconnect traces and vias. These openings are simultaneously filled with a metal, conventionally aluminum with more recent developments using copper. The created metal interconnects serve to interconnect active and/or passive elements of the Integrated Circuit.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed.
The invention concentrates on using copper as a metal interconnect medium, a dual damascene pattern of copper is first created and annealed. After this, and of critical importance to the invention, a thin layer of oxide is deposited as a cap layer after which a layer of etch stop material is deposited over the thin layer of oxide.
U.S. Pat. No. 6,406,996 B1 (Bernard et al.) shows copper dual damascene interconnects with sub cap and cap layers.
U.S. Pat. No. 6,169,028 B1 (Wang et al.) shows an oxide cap over a copper dual damascene interconnect.
U.S. Pat. No. 6,309,970 B1 (Ito et al.) shows a copper oxide on a copper surface.
U.S. Pat. No. 6,274,499 B1 (Gupta et al.) shows a dielectric cap over an interconnect.